Electronic Engineer and self-employed consultant, Physics degree, working in VHDL, Verilog, and C++, primarily in FPGA and ASIC design. I've written two compilers, including one which generates Verilog (9-pass, about 50K lines of C++). I'll add VHDL output if/when I get some spare time. I also have experience in SystemC and Specman/'e'.

I occasionally write JavaScript, and odd bits of HTML/PHP/Ajax, when I've got nothing better to do, primarily to generate and display SVG images.

Always looking for new opportunities - mail me if you want to discuss anything; I'm on sa212+stackoverflow at cyconix dotcom.